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25015 FPGA4: C/C++ to Verilog using FPGA SmartHLS Compiler (August 2025)

In this class, you will gain the skills to verify functionality and analyze the performance of your designs, expedite your design cycle by leveraging the capabilities of the SmartHLS compiler.

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About this course

This is a recording of the course "25015 FPGA4: C/C++ to Verilog using FPGA SmartHLS Compiler " from the 2025 MASTERs Conference.

This class introduces Microchip's High-Level Synthesis compiler (SmartHLS), which demonstrates how to convert C/C++ code into Verilog code raising the FPGA design abstraction to C/C++ code level. This class also demonstrates the process of integrating SmartHLS generated blocks into the FPGA design flow, shows the features of SmartHLS pragmas and built-in C++ libraries, and verify functionality and analyze system performance. By the end of the class, you will gain the skills to verify functionality and analyze the performance of your designs, expedite your design cycle by leveraging the capabilities of the SmartHLS compiler.

Prerequisites:

No prior knowledge of High-Level Synthesis is need; however basic understanding of FPGA design flow is needed.

Curriculum62 min

  • About this course
  • Class Overview
  • Syllabus & Downloads
  • Introduction 4 min
  • What is High-level Synthesis (HLS)? 6 min
  • When Should You Use HLS? 5 min
  • Software to Hardware Compilation 2 min
  • SmartHLS™ Compiler 7 min
  • SmartHLS™: Reviewing Reports 2 min
  • Software Simulation 3 min
  • LAB1: Basic Implementation and Simulation 1 min
  • Pragmas and C++ Libraries 7 min
  • Acceleration by Parallelism 4 min
  • LAB2: Loop Pipelining
  • Streaming Parallelism 6 min
  • Line Buffer 6 min
  • LAB3: Streaming Hardware 1 min
  • Lab4: Importing to Libero SoC 3 min
  • SmartHLS™ Documentation & Useful Links 3 min
  • Summary 2 min
  • Complete Recording
  • 25015 FPGA4 (64 min)
  • Feedback and Discussion

About this course

This is a recording of the course "25015 FPGA4: C/C++ to Verilog using FPGA SmartHLS Compiler " from the 2025 MASTERs Conference.

This class introduces Microchip's High-Level Synthesis compiler (SmartHLS), which demonstrates how to convert C/C++ code into Verilog code raising the FPGA design abstraction to C/C++ code level. This class also demonstrates the process of integrating SmartHLS generated blocks into the FPGA design flow, shows the features of SmartHLS pragmas and built-in C++ libraries, and verify functionality and analyze system performance. By the end of the class, you will gain the skills to verify functionality and analyze the performance of your designs, expedite your design cycle by leveraging the capabilities of the SmartHLS compiler.

Prerequisites:

No prior knowledge of High-Level Synthesis is need; however basic understanding of FPGA design flow is needed.

Curriculum62 min

  • About this course
  • Class Overview
  • Syllabus & Downloads
  • Introduction 4 min
  • What is High-level Synthesis (HLS)? 6 min
  • When Should You Use HLS? 5 min
  • Software to Hardware Compilation 2 min
  • SmartHLS™ Compiler 7 min
  • SmartHLS™: Reviewing Reports 2 min
  • Software Simulation 3 min
  • LAB1: Basic Implementation and Simulation 1 min
  • Pragmas and C++ Libraries 7 min
  • Acceleration by Parallelism 4 min
  • LAB2: Loop Pipelining
  • Streaming Parallelism 6 min
  • Line Buffer 6 min
  • LAB3: Streaming Hardware 1 min
  • Lab4: Importing to Libero SoC 3 min
  • SmartHLS™ Documentation & Useful Links 3 min
  • Summary 2 min
  • Complete Recording
  • 25015 FPGA4 (64 min)
  • Feedback and Discussion