25101 PCB8: Accelerating Microchip based Power Electronics Design Using Siemens EDA Tools (August 2025)

This class demonstrates how today’s integrated design and verification solutions enable engineers to create more efficient PCB designs. No online material!

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About this course

Using a Microchip reference design, this presentation demonstrates how today’s integrated design and verification solutions enable engineers to create more efficient PCB designs. Microchip and Siemens recognize the need for practical methods to improve efficiency and shorten development cycles. Both companies observe significant acceleration through the utilization of validated design templates, automation, and verification. For this reason, the presentation combines best-practice circuits with comprehensive validation methods. The proposed method addresses signal integrity, power integrity, and thermal performance, demonstrating how modern PCB design flows enhance product robustness and reliability. As an example of robustness and reliability criteria, setup and hold time margins for signal integrity, Z-parameter distribution for power integrity, and turn-on and off energies for thermal performance can be examined. Typically, validation and verification methods identify issues only after a design falls out of specification. In contrast, automated design space exploration identifies potential solutions. This transforms traditional finger pointing into a proactive engineering solution. The concept of this integrated and proactive engineering solution is illustrated through a practical Microchip example. Starting with a Microchip reference design, routing and placement changes are introduced. These changes are then verified using electromagnetic solvers. As a result, board parasitics such as resistance, inductance, capacitance and conductance are extracted and back annotated to the schematic. This process allows verification of the board switching behaviour and accurately predicts electrical losses. After understanding the manual steps, the prepared simulation templates are used to fully automate the change and verification process, demonstrated on a placement optimization case study to reduce switching losses.

About this course

Using a Microchip reference design, this presentation demonstrates how today’s integrated design and verification solutions enable engineers to create more efficient PCB designs. Microchip and Siemens recognize the need for practical methods to improve efficiency and shorten development cycles. Both companies observe significant acceleration through the utilization of validated design templates, automation, and verification. For this reason, the presentation combines best-practice circuits with comprehensive validation methods. The proposed method addresses signal integrity, power integrity, and thermal performance, demonstrating how modern PCB design flows enhance product robustness and reliability. As an example of robustness and reliability criteria, setup and hold time margins for signal integrity, Z-parameter distribution for power integrity, and turn-on and off energies for thermal performance can be examined. Typically, validation and verification methods identify issues only after a design falls out of specification. In contrast, automated design space exploration identifies potential solutions. This transforms traditional finger pointing into a proactive engineering solution. The concept of this integrated and proactive engineering solution is illustrated through a practical Microchip example. Starting with a Microchip reference design, routing and placement changes are introduced. These changes are then verified using electromagnetic solvers. As a result, board parasitics such as resistance, inductance, capacitance and conductance are extracted and back annotated to the schematic. This process allows verification of the board switching behaviour and accurately predicts electrical losses. After understanding the manual steps, the prepared simulation templates are used to fully automate the change and verification process, demonstrated on a placement optimization case study to reduce switching losses.