This video is still being processed. Please check back later and refresh the page.

Uh oh! Something went wrong, please try again.

dsPIC33A® 12-bit 40MSPS ADC

In this course you will learn about the dsPIC33A ADC, a high-performance analog-to-digital converter designed for advanced embedded control systems.

rate limit

Code not recognized.

About this course

The dsPIC33AK512MPS512 family of devices has 5 high-speed (40 MSPs), 12-bit Analog-to-Digital Converters (ADCs) that feature low conversion latency, high resolution, and oversampling capabilities to improve performance in AC/DC and DC/DC power converters, as well as general-purpose Digital Signal Processing (DSP) applications.

This new ADC architecture not only enhances existing features and operating modes, it also offers significantly greater flexibility and customization. This enables you to tailor the ADC’s performance to meet the specific requirements of your application with greater precision and efficiency.

Curriculum

  • Class Overview
  • Architecture
  • Introduction
  • High-Level Overview
  • Analog-to-Digital Converter (ADC) Core
  • Data Channels
  • Data Channel Configuration
  • Data Channel Natural Priority
  • Analog Inputs
  • Data Channels
  • Data Channel Overview
  • Introduction
  • Sampling Modes
  • Conversion Triggers
  • Special Features
  • Introduction
  • Digital Comparators
  • Secondary Accumulators
  • Gain and Offset Calibration​
  • Sleep and Idle Modes
  • UREF Voltage Reference​
  • Common Pitfalls
  • Overview
  • ADC Input and Data Format
  • Crosstalk
  • Input Model
  • Signal to Noise Ratio and Effective Number of Bits (ENOB)
  • Signal-to Noise Ratio - Oversampling
  • Performance and Timing
  • Overview
  • Pipelined Architecture
  • ADC Latency
  • Latency Considerations
  • Conversion Trigger Examples
  • Single Conversion Trigger Best Case: Trigger to Data Ready
  • Single Conversion ADC After Data Ready
  • Single Conversion Trigger Best Case
  • Single Conversion Trigger - Worst Case
  • Multi-channel Conversion Trigger
  • Single-Channel Periodic Conversion
  • Conversion Trigger Guidance
  • Conversion Trigger Guidance (Continued)
  • Throughput
  • Oversampling Throughput
  • Oversampling Metrics
  • Demo Examples
  • Demo Examples continued
  • DSP Performance
  • Performance Summary
  • System Resources
  • Introduction
  • DMA Support
  • Analog-to-Digital Converter (ADC) Data Channel Interrupts
  • Reference Materials
  • Further Reading and Training
  • Feature and Benefits
  • Code Examples
  • Demo Boards/Hardware

About this course

The dsPIC33AK512MPS512 family of devices has 5 high-speed (40 MSPs), 12-bit Analog-to-Digital Converters (ADCs) that feature low conversion latency, high resolution, and oversampling capabilities to improve performance in AC/DC and DC/DC power converters, as well as general-purpose Digital Signal Processing (DSP) applications.

This new ADC architecture not only enhances existing features and operating modes, it also offers significantly greater flexibility and customization. This enables you to tailor the ADC’s performance to meet the specific requirements of your application with greater precision and efficiency.

Curriculum

  • Class Overview
  • Architecture
  • Introduction
  • High-Level Overview
  • Analog-to-Digital Converter (ADC) Core
  • Data Channels
  • Data Channel Configuration
  • Data Channel Natural Priority
  • Analog Inputs
  • Data Channels
  • Data Channel Overview
  • Introduction
  • Sampling Modes
  • Conversion Triggers
  • Special Features
  • Introduction
  • Digital Comparators
  • Secondary Accumulators
  • Gain and Offset Calibration​
  • Sleep and Idle Modes
  • UREF Voltage Reference​
  • Common Pitfalls
  • Overview
  • ADC Input and Data Format
  • Crosstalk
  • Input Model
  • Signal to Noise Ratio and Effective Number of Bits (ENOB)
  • Signal-to Noise Ratio - Oversampling
  • Performance and Timing
  • Overview
  • Pipelined Architecture
  • ADC Latency
  • Latency Considerations
  • Conversion Trigger Examples
  • Single Conversion Trigger Best Case: Trigger to Data Ready
  • Single Conversion ADC After Data Ready
  • Single Conversion Trigger Best Case
  • Single Conversion Trigger - Worst Case
  • Multi-channel Conversion Trigger
  • Single-Channel Periodic Conversion
  • Conversion Trigger Guidance
  • Conversion Trigger Guidance (Continued)
  • Throughput
  • Oversampling Throughput
  • Oversampling Metrics
  • Demo Examples
  • Demo Examples continued
  • DSP Performance
  • Performance Summary
  • System Resources
  • Introduction
  • DMA Support
  • Analog-to-Digital Converter (ADC) Data Channel Interrupts
  • Reference Materials
  • Further Reading and Training
  • Feature and Benefits
  • Code Examples
  • Demo Boards/Hardware