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About this course
- Class Overview
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Syllabus & Downloads
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Introduction 3 min
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Customer's Current Workflow 1 min
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Integrated Workflow 4 min
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Integrated Workflow - FIL Set up and Demo 22 min
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MathWorks FPGA In Loop Workflow 14 min
- Complete Recording
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Microchip and MathWorks - full recording(45 min)
- Feedback
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Microchip and MathWorks - Integrated FIL and IP Core Generation Workflow
Puneet Kuma and Max Bucklin present: Microchip and MathWorks - Integrated FIL and IP Core Generation Workflow (February 2025)
Max Bucklin from Microchips Aerospace and Defense Group, along with Puneet Kuma, presented a session on Microchip and MathWorks integrated FPGA workflows. They discussed the FPGA in the Loop (FIL) workflow, which supports various development kits and the IP core generation workflow for PolarFire SoC kits. The session included a demo showcasing the integration of MATLAB and Simulink with Microchip's FPGA boards, highlighting the process of generating HDL code, verifying it through co-simulation, and implementing it on hardware. They also introduced upcoming workflows for critical path estimation and processor in the loop, emphasizing the advantages of using Microchip's low-power, secure FPGAs for digital signal processing, control systems, and vision-based applications. The presentation concluded with a Q&A session.