- Class Overview
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Syllabus & Downloads
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Introduction 1 min
- RISC-V Overview
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Overview 2 min
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RISC-V Registers and Instruction Set 7 min
- Microchip's Soft RISC-V CPU Offering
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Overview 1 min
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Mi-V RV32 Core Architecture 7 min
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AMBA Bus Interfaces 14 min
- Mi-V Ecosystem
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Mi-V Ecosystem 3 min
- Building a RISC-V System in PolarFire® / SoC
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Configure IP Catalog cores 14 min
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Simulate the design 11 min
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Constraining the Mi-V Design 2 min
- RISC-V Firmware Development
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RISC-V Firmware Development 3 min
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Mi-V Baremetal Examples 6 min
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SoftConsole® Project Settings 3 min
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Debugging MiV Baremetal Applications 4 min
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Production Programming 4 min
- More Information
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Useful Links
- Complete Recording
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RISC-V (85 min)
- Feedback and Discussion
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Get in contact with the presentation team
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We need your feedback
RISC-V for PolarFire® & PolarFire® SoC (February 2026)
This course guides you through configuring, integrating, and developing RISC-V systems on PolarFire® and PolarFire® SoC platforms, enabling you to design, simulate, debug, and deploy Mi‑V™–based solutions with confidence. This course is the foundation for the Hands-On Class.
This course provides a comprehensive walkthrough of designing, configuring, and developing RISC-V–based systems on Microchip PolarFire® and PolarFire® SoC devices using the Mi-V™ soft processor ecosystem. It begins by establishing a clear understanding of what RISC-V is—and what it is not—highlighting its open instruction set architecture, extensibility through standard extensions, and broad industry adoption. The course explains why RISC-V is particularly well suited for FPGA- and SoC-based designs, emphasizing transparency, long-term software stability, and freedom from licensing constraints.
Building on this foundation, the training introduces Microchip’s Mi-V™ RV32 architecture, including its core (hart) and subsystem composition, supported extensions, interrupts, tightly coupled memory (TCM), instruction cache options, and debug capabilities. A significant portion of the course is dedicated to practical system construction using Libero® SoC, covering Mi-V™ core configuration, memory selection, reset behavior, ECC considerations, and system integration through SmartDesign. Learners gain deep insight into AMBA® bus architectures such as AXI, AHB-Lite, and APB, including when to use each interface and how to leverage Microchip bus interconnects, bridges, and converters.
The course further explores the Mi-V™ ecosystem holistically, introducing relevant IP cores, peripheral integration options, and the Mi-V™ Extended Subsystem Solution (ESS) for simplified designs. It then moves into firmware development using SoftConsole, explaining project structure, hardware abstraction layers, drivers, and linker script alignment with hardware memory maps. Simulation, debugging, and deployment workflows are demonstrated, from waveform-based instruction tracing in QuestaSim to on-hardware debugging and production programming. By the end of the course, learners are equipped to design, simulate, debug, and deploy reliable RISC-V systems on PolarFire® platforms with confidence.
Course Objectives
- Understand the RISC-V instruction set architecture and its relevance to PolarFire® and PolarFire® SoC designs
- Configure and integrate the Mi-V™ RV32 core using Libero® SoC SmartDesign
- Select and connect appropriate memory, bus interfaces, and peripherals for a complete system
- Develop and debug bare-metal firmware using SoftConsole and Mi-V™ HALs
- Simulate, constrain, and deploy RISC-V designs efficiently on real hardware
| Course title | RISC-V for PolarFire® & PolarFire® SoC |
| Presenter(s) | Garo Janir / Contact: garo.janir@microchip.com |
| Published / Updated Time | March 2026 |