RISC-V for PolarFire® & PolarFire® SoC Hands-on-Lab (March 2026)

Garo Janir guides you through a hands-on RISC-V lab on PolarFire® and PolarFire® SoC, enabling you to design, simulate, program, and debug a complete bare-metal system from Libero® SoC to live hardware. This is Part 2 of the RISC-V training.

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About this course

This course builds directly on the foundational RISC-V for PolarFire® and PolarFire® SoC training and transitions you into a fully guided, end-to-end hands-on lab experience. You will design, simulate, program, and debug a complete RISC-V–based system using the PolarFire® SoC platform, with a strong focus on practical implementation rather than theory alone. Starting from project creation in Libero® SoC, the course walks through building a Mi-V RISC-V processor subsystem, integrating key IP cores such as CoreAPB3, CoreGPIO, CoreTimer, CoreUARTapb, CoreJTAGDebug, and PolarFire® SRAM with an AHB-Lite interface. You will configure clocks using the Clock Conditioning Circuit (CCC), define memory maps, and apply both timing and physical constraints.

The lab continues with functional simulation using Questa® SIM, where you will observe AHB-Lite and APB transactions, validate timer interrupts, and verify GPIO behavior. You will then generate FPGA programming data, initialize on-chip SRAM using the SmartDebug Memory Initialization tool, and deploy the design to supported hardware kits, including the Discovery Kit, Icicle Kit, and Splash Kit. Finally, the course guides you through creating, building, and debugging a bare-metal RISC-V application in SoftConsole, enabling you to interact with peripherals, handle interrupts, and observe real-time UART output and LED behavior on hardware. By the end of this lab, you will have hands-on experience with the complete RISC-V design flow on PolarFire® SoC, from IP integration to live debugging on silicon.

Course Objectives

  • Build a Mi-V RISC-V–based subsystem in Libero® SoC using PolarFire® and PolarFire® SoC IP cores
  • Configure and connect AHB-Lite and APB3 interfaces to memory and peripherals
  • Simulate RISC-V designs and analyze bus transactions and interrupts in Questa® SIM
  • Program and initialize on-chip SRAM and deploy designs to supported PolarFire® SoC kits
  • Develop and debug a bare-metal RISC-V application using SoftConsole and hardware debugging
Course title RISC-V for PolarFire® & PolarFire® SoC Hands-on-Lab
Presenter(s) Garo Janir / Contact: Garo.Janir@microchip.com
Published / Updated Time March 2026

Curriculum47 min

  • Class Overview
  • Syllabus & Downloads
  • Lab Objectives 2 min
  • Launching Libero SoC and Creating Mi-V Project 4 min
  • Setting the Cores in our Smart Design 8 min
  • Simulating the Design 9 min
  • Timing & Physical Constraints 3 min
  • Bitstream Generation and Programming 6 min
  • Mi-V Baremetal Evelopment with SoftConsole 15 min
  • Complete Recording
  • RISC_V Hands-On (48 min)
  • Feedback and Discussion
  • Get in contact with the presentation team
  • We need your feedback

About this course

This course builds directly on the foundational RISC-V for PolarFire® and PolarFire® SoC training and transitions you into a fully guided, end-to-end hands-on lab experience. You will design, simulate, program, and debug a complete RISC-V–based system using the PolarFire® SoC platform, with a strong focus on practical implementation rather than theory alone. Starting from project creation in Libero® SoC, the course walks through building a Mi-V RISC-V processor subsystem, integrating key IP cores such as CoreAPB3, CoreGPIO, CoreTimer, CoreUARTapb, CoreJTAGDebug, and PolarFire® SRAM with an AHB-Lite interface. You will configure clocks using the Clock Conditioning Circuit (CCC), define memory maps, and apply both timing and physical constraints.

The lab continues with functional simulation using Questa® SIM, where you will observe AHB-Lite and APB transactions, validate timer interrupts, and verify GPIO behavior. You will then generate FPGA programming data, initialize on-chip SRAM using the SmartDebug Memory Initialization tool, and deploy the design to supported hardware kits, including the Discovery Kit, Icicle Kit, and Splash Kit. Finally, the course guides you through creating, building, and debugging a bare-metal RISC-V application in SoftConsole, enabling you to interact with peripherals, handle interrupts, and observe real-time UART output and LED behavior on hardware. By the end of this lab, you will have hands-on experience with the complete RISC-V design flow on PolarFire® SoC, from IP integration to live debugging on silicon.

Course Objectives

  • Build a Mi-V RISC-V–based subsystem in Libero® SoC using PolarFire® and PolarFire® SoC IP cores
  • Configure and connect AHB-Lite and APB3 interfaces to memory and peripherals
  • Simulate RISC-V designs and analyze bus transactions and interrupts in Questa® SIM
  • Program and initialize on-chip SRAM and deploy designs to supported PolarFire® SoC kits
  • Develop and debug a bare-metal RISC-V application using SoftConsole and hardware debugging
Course title RISC-V for PolarFire® & PolarFire® SoC Hands-on-Lab
Presenter(s) Garo Janir / Contact: Garo.Janir@microchip.com
Published / Updated Time March 2026

Curriculum47 min

  • Class Overview
  • Syllabus & Downloads
  • Lab Objectives 2 min
  • Launching Libero SoC and Creating Mi-V Project 4 min
  • Setting the Cores in our Smart Design 8 min
  • Simulating the Design 9 min
  • Timing & Physical Constraints 3 min
  • Bitstream Generation and Programming 6 min
  • Mi-V Baremetal Evelopment with SoftConsole 15 min
  • Complete Recording
  • RISC_V Hands-On (48 min)
  • Feedback and Discussion
  • Get in contact with the presentation team
  • We need your feedback